It is well known that in integrated circuit operation, fault conditions or failures can cause extremely faint photon emissions. These photon emissions can be detected by an emission microscope such as the one described in U.S. Pat. No. 4,680,635 to Khurana. Co-pending U.S. patent application Ser. No. 08/555,186 discloses a workstation for analyzing IC fault conditions. Images obtained which show faults or failures based upon the resulting emissions are referred to as fault contrast images.
It is also well known that during integrated circuit operation, an electron microscope can detect differing logic levels of a node in an integrated circuit. For example, a node which is at +5 volts will tend to absorb electrons emitted from an electron microscope (appearing dark in a black and white image), whereas, a node which is at 0 volts will tend to reflect electrons emitted from the electron microscope (appearing light in a black and white image). Therefore, an image obtained will depend upon the voltage levels at the various nodes of the integrated circuit. This is referred to as voltage contrast imaging. U.S. Pat. No. 4,772,846 to Reeds discloses an apparatus for chip testing by voltage contrast electron microscopy.
A method of failure analysis using voltage contrast imaging utilizes image subtraction. Image subtraction involves obtaining a first voltage contrast image of an integrated circuit operating under a first set of input conditions, then obtaining a second voltage contrast image of the integrated circuit operating under a second set of input conditions. Then, one image is subtracted from the other image. The subtraction operation may be performed by storing each image in digital form and then using software to perform the subtraction operation on corresponding pixels from each image. The resulting image is representative of nodes of the integrated circuit that changed logic levels when the first set of inputs changed to the second set of inputs; any part of the integrated circuit which did not change logic levels will be removed from the resulting image by the subtract operation. The resulting image, however, suffers from a drawback in that only one direction of logic change is represented. For example, if the node is at a high logic level (absorbs electrons) in the first image and is at a low logic level in the second image (reflects electrons) and the first image is subtracted from the second image, the node will appear to have changed states. However, if a node is at a low logic level (reflects electrons) in the first image and is at a high logic level in the second image (absorbs electrons) and the first image is subtracted from the second image, the node will not appear to have changed states. This is because subtracting the image representing the reflected electrons (a light area in the black and white image) will not affect the appearance of the already dark node in the resulting image.
Alternately, the first image and the second image may be combined using the exclusive OR operation. The resulting image will then show logic changes in both directions. However, both of these methods suffer from the drawback that the resulting image does not show the logic states of unchanged nodes. When tracking failures such as a saturated transistor resulting from a logic short somewhere else, all logic states, both static and transitional, need to be represented simultaneously in order to perform an expedient analysis.
Therefore, what is needed is a method and apparatus for failure tracking and analysis that does not suffer from the above described drawbacks.